Fault-Tolerance of the Iterative Cell Array Switch for Hybrid Redundancy

The technique of hybrid redundancy has been used to protect those portions of a digital system which have to be made ultrareliable. Siewiorek and McCluskey have presented a new switch design for hybrid redundancy which is shown to be of less complexity than other switch designs presented in the literature. The possibility of increasing the overall system reliability is examined, considering schemes which will allow the switch to be tolerant of a certain number of faults in the hardware. The use of fail-safe logic together with a coding scheme has been found to be an effective way to increase the fault-tolerance of the switch. The fault-tolerance could also be achieved through the use of classical protection schemes such as triple modular redundancy (TMR). The two fault-tolerant strategies are compared using reliability, cost, and speed parameters as basis for comparison. A reliability analysis of the various system configurations has indicated that it is advantageous to increase the fault-tolerance, as a significant improvement of the overall system reliability is obtained. However, an optimum fault-tolerance exists, beyond which degradation of the system results. The question of whether adding spares to a system will always improve the system reliability is studied and it is found that this is not always the case. Finally, the implementation of error detection circuitry using self-checking checkers is discussed, together with the possibility of the construction of a fault-tolerant voter.